# Multiplexer

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A multiplexer is a combinational circuit that has ‘n’ input lines, ‘m’ selection lines and single output line. It is also known as many to one circuit. Multiplexer select binary information from many input lines and routes it to single output line. Its output is depending on value of select inputs or select lines.

For N input lines, m=log n (base2) selection lines, or we can say that for 2n input lines, m selection lines are required.

The multiplexer, abbreviation to “MUX”.

Multiplexers work as a Data selector circuit”. It select data from many input lines and routes it to single output line.

The above diagram is a multiplexer circuit having 4 input lines, one enable input , single output line and 2 select line. Select line we calculate using m=log n (base2) formula, where n is the no. of input and m is the select line. We can select any one of the input by moving the dialer we can have a input at the output. Dialer move and select input depend on the value of select line.

Multiplexer Is available in the form of IC (integrated circuit). It is a MSI (medium scale integrated circuit ). For different multiplexer circuits different IC’s are available. We can implement various combinational circuits using multiplexer IC like half adder, full adder, Subtractor etc.

1. It reduces the number of wires.
2. Hence, it reduces the circuit complexity, cost and size.
3. We can implement many combinational circuits using MUX.
4. It simplifies the logic design.

It does not need the k-maps and simplification.

## Classification of Multiplexer

Multiplexer may be classified as under:

1. 2:1 Multiplexer
2. 4:1 Multiplexer
3. 8:1 Multiplexer
4. 16:1 Multiplexer

## 2:1 Multiplexer

The block diagram of 2:1 multiplexer has been shown in figure. It has two data inputs Io and I1 , one select input line (S), enable input (E) and one output. The output of the circuit is depends on the value of select line. The truth table of 2:1 mux has been shown below.

From the above truth table, we enable input E=1 circuit operate and we get the output

Therefore, The logical expression for output Y is as follows:

Y= ES’Io + ESI1 or Y = E(S’Io + SI1)

Using the above logical expression, do realization using gates

For more detail watch my YouTube video

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